1. Field of the Invention
The present invention generally relates to semiconductor memory devices and, more particularly, to a semiconductor memory device adapted for preventing a test mode operation from undesirably occurring. The present invention has particular applicability to static random access memories (SRAMs).
2. Description of the Background Art
Generally, a pre-shipment test insuring whether manufactured semiconductor integrated circuit devices can achieve desired functions or not is performed on semiconductor integrated circuit devices including a semiconductor memory or the like, before the shipment from the factory. In the pre-shipment test, a semiconductor memory, for example, is operated in an externally designated test mode. That is, some test mode signal is externally applied to the semiconductor memory, leading the semiconductor memory to carry out a test mode operation in response to the applied test mode signal.
In general, the pre-shipment test should be performed only in the manufacturing factories of semiconductor devices. For the user of the semiconductor device, it is not preferable for the shipped semiconductor device to be operated in the test mode for the pre-shipment test. However, depending on the case, the test mode operation may be caused unfavorably. In the following description, the explanation will first be made with a semiconductor memory on the reason for this unfavorable test mode operation being caused.
FIG. 6 is a block diagram of a static random access memory (hereinafter referred to as a "SRAM") showing a background of the present invention. Referring to FIG. 6, a SRAM 101 includes a plurality n of memory blocks BK1 to BKn and a block selector circuit 8 for selecting a memory block to be accessed. One of the memory blocks BK1 to BKn, for example, memory block BK1 includes a memory cell array 11 provided with memory cells arranged in rows and columns (not shown), a bit line loading circuit 171, a multiplexer 21 for selecting a bit line pair to be accessed, a write buffer 31 for data writing and a sense amplifier 41 for data reading. Similar circuit configurations are provided in other memory blocks BK2 to BKn.
The SRAM 101 further includes a row address buffer 51 receiving externally applied row address signals RA, a column address buffer 52 receiving externally applied column address signals CA, a block address buffer 53 receiving externally applied block address signals BA, a row decoder decoding row address signals RA, a column decoder 7 decoding column address signals CA, block selector 8 selecting a block to be accessed by decoding the block address signals BA, a data input buffer 55 receiving an input data signal DI, a data output buffer 56 providing an output data signal DO and a read/write control circuit 54 operating responsive to an externally applied chip selection signal/CS and a write enable signal/WE.
Next, a normal access operation will be described. When memory block BK1 is accessed, for example, the block address signal BA for designating memory block BK1 is applied to block selector circuit 8. Block selector circuit 8 decodes the applied block address signal BA to selectively activate only write buffer 31 and sense amplifier 41. In data reading, row decoder 6 activates one of word lines (not shown) in memory cell array 11 in response to the row address signal RA. Column decoder 7 selects one of the columns in memory cell array 11 in response to the column address signal CA. Therefore, a data signal stored in the memory cell designated by row decoder 6 and column decoder 7 is applied to sense amplifier 41 through multiplexer 21. The data signal amplified by sense amplifier 41 is provided as the output data DO through data output buffer 56.
In data writing, an input data DI is applied to write buffer 31 through input buffer 55. Column decoder 7 selects one of the columns in memory cell array 11 in response to the column address signals CA. Row decoder 6 activates one of the word lines in memory cell array 11 in response to the row address signal RA. Therefore, write buffer 31 writes a data signal in the memory cell designated by row decoder 6 and column decoder 7 through multiplexer 21.
FIG. 7 is a schematic diagram of a peripheral circuit of memory cell array 11 shown in FIG. 6. Referring to FIG. 7, for simplification of representation, only four memory cells 24a to 24d in memory cell array 11 are shown. Memory cells 24a and 24c are connected between bit lines 20a and 20b. Memory cells 24b and 24d are connected between bit lines 21a and 2lb.
Bit line loading circuit 171 includes NMOS transistors 25a, 25b, 26a and 26b each connected between a power supply potential Vcc and the corresponding one of bit lines 20a, 20b, 21a and 2lb, respectively. Multiplexer 21 includes NMOS transistors 27a and 27b connected between an I/O line pair 29a, 29b and bit lines 20a, 20b and also includes NMOS transistors 28b and 28b connected between an I/O line pair 29a, 29b and bit lines 21a, 2lb, respectively. I/O line pair 29a and 29b are connected to the input of sense amplifier 41 and the output of write buffer 31, respectively.
Row decoder 6 selectively activates one of word lines WL0 and WL1 connected to the memory cell to be accessed. Memory cells 24a and 24b connected to word line WL0 constitute one memory cell row. When word line WL0 is activated, the memory cell row including memory cells 24a and 24b is accessed. Column decoder 7 activates one of column selection signals Y0 and Y1 for selecting a memory cell column to be accessed. When the column selection signal Y0 is activated, for example, transistors 27a and 27b are turned on, whereby the memory cell column including memory cells 24a and 24c is accessed.
FIG. 8 is a schematic diagram of a circuit showing one example of the memory cell of FIG. 7. Referring to FIG. 8, this memory cell MC1 (for example, 24a of FIG. 7) includes NMOS transistors 41a and 4lb, resistances 43a and 43b as high resistance loads and NMOS transistors 42a and 42b as access gates.
FIG. 9 is a schematic diagram of a circuit showing another example of the memory cell of FIG. 7. Referring to FIG. 9, this memory cell MC2 includes NMOS transistors 41a and 4lb, PMOS transistors 44a and 44b acting as loads and NMOS transistors 42a and 42 as access gates.
FIG. 10 is a timing chart showing a reading operation of memory cell 24a of FIG. 7. Referring to FIG. 10, an abscissa denotes the passage of time and an ordinate denotes a potential (volt). A line ADi shows a change in input signals of row address buffer 51 column address buffer 52. A line ADo shows a change in output signals of row and column address buffers 51 and 52. A line WL shows a change in word line WL0 connected to memory cell 24a. A line I/O shows a change in the potential of I/O line pair 29a and 29b. A line SAo shows a change in the output voltage of sense amplifier 41. A line Do shows a change in the output voltage of data output buffer 56.
At time t0, the input address signal ADi is changed, whereby the output signal ADo of address buffers 51 and 52 is changed in at time t1. At time t2, a potential of word line WL0 changes, whereby a data signal stored in memory cell 24a is transmitted to bit line pair 20a and 20b. In addition, the column selection signal Y0 provided from the column decoder 7 attains a high level, whereby transistors 27a and 27b are turned on. Consequently, at time t3, potentials of I/O line pair 29a and 29b are changed.
At time t4, sense amplifier 41 is activated responsive to a control signal supplied by read/write control circuit 54, whereby the data signal is amplified by sense amplifier 41. Therefore, at time t5, the output signal Do of data output buffer 56 is changed according to the data read out from memory cell 24a.
In the foregoing pre-shipment test, an accelerated test of a semiconductor device is generally performed. The accelerated test is also performed on the SRAM by applying an environmental stress (temperature, humidity, vibration or the like) and an electric stress (voltage, current or the like) to the SRAM. That is, after the above-described stress is applied to the SRAM, data writing and data reading are performed on that SRAM. Data writing and data reading are repeatedly performed on all of the memory cells in the memory cell array, whereby a match of written data and read data is ensured. When a match of a written data and a read data is not detected, the SRAM is scrapped as defective.
In recent years, the following improvement is effected to shorten the test hour, since it takes very long time to perform the above-described data writing and data reading on each of the memory cells, and to read out a match, respectively.
Referring again to FIG. 6, the SRAM 101 further includes a match detecting circuit 5 connected to receive data signals provided from sense amplifiers 41 to 4n. When a test mode signal TM is externally applied through a spare terminal 57, match detecting circuit 5, write buffers 31 to 3n and sense amplifiers 41 to 4n are enabled. As a result, a common input signal DI can be written in the memory cells of the corresponding address in memory cell arrays 11 to 1n. In addition, data signals read out from the memory cell of the corresponding address in each of memory cell arrays 11 to n can be simultaneously applied to match detecting circuit 5 through sense amplifiers 41 to 4n. A signal showing a match detection result is provided through data output buffer 56 in the test mode.
During the period of the application of the test mode signal TM, the row address signals RA and the column address signals CA are repeatedly applied, the data signal is written in the memory cell of the corresponding address in each of memory cell arrays 11 to 1n, and the stored data signals are read out. In match detecting circuit 5, when a match between the written data and the read data is detected in every address, the SRAM of which is determined as "effective". Thus, since repetition of the data writing and the data reading can be performed in parallel on all of the memory cell arrays 11 to in by using match detecting circuit 5, time required for the test is reduced.
In SRAM 101 shown in FIG. 6, spare terminal 57 is employed to designate the test mode. When the SRAM does not have a spare terminal, a high voltage detecting circuit 59 shown in FIG. 11 is provided.
FIG. 11 is a block diagram of an another example of the SRAM showing the background of the present invention. Referring to FIG. 11, this SRAM 102 includes high voltage detecting circuit 59 connected to the most significant terminal 58 of external terminals receiving the block address signals BA. When a test mode is externally designated, a high voltage signal HV over a power supply potential Vcc is applied through terminal 58. High voltage detecting circuit 59 provides a test mode signal TM in response to the application of the high voltage signal HV. The test mode signal TM is applied to match detecting circuit 5, write buffers 31 to 3n and sense amplifiers 41 to 4n.
Terminal 58 for receiving the most significant bit of the block address signals BA is used to designate a memory block in normal operation. In the test mode, all of the memory blocks are accessed as described above. Therefore, since the designation of the memory block is not required, terminal 58 can be used to externally designate the test mode in the test mode. That is, no problem is caused in the test mode by the application of the high voltage signal HV through terminal 58.
A similar test operation to that of the SRAM 101 shown in FIG. 6, that is a match detecting operation by the match detecting circuit 5 is repeated after the provision of the test mode signal TM from high voltage detecting circuit 59.
FIG. 12 is a block diagram showing yet another example of the SRAM showing the background of the present invention. Referring to FIG. 12, a SRAM 103 includes a high voltage detecting circuit 60 connected to a terminal 62 for receiving a write enable signal/WE, and a test mode signal holding circuit 61 connected to terminal 58 for receiving the most significant bit of the block address signals BA. When the test mode is externally designated, the high voltage signal HV is applied through terminal 62. High voltage detecting circuit 60 provides a holding signal HD in response to the high voltage signal HV. Test mode signal holding circuit 61 holds a test mode signal TM' applied through terminal 58 in response to the application of the holding signal HD. The held signal is provided from test mode signal holding circuit 61 as the test mode signal TM.
In the SRAM 103 of FIG. 12, high voltage detecting circuit 60 and test mode signal holding circuit 61 are employed to externally designate the test mode. After the test mode signal TM' is once held in test mode signal holding circuit 61, the test mode signal TM is continuously applied to match detecting circuit 5, write buffers 31 to 3n and sense amplifiers 41 to 4n. Therefore, a successive application of the high voltage signal HV to terminal 62 is not necessary after the completion of the designation of the test mode. A match detecting operation by match detecting circuit 5 is performed in the same manner as the SRAM 101 of FIG. 6.
FIG. 13 is a schematic diagram of high voltage detecting circuit 60 shown in FIG. 12. Referring to FIG. 13, high voltage detecting circuit 60 includes an inverter 78 for a level determination and NMOS transistors 86, 87 and 88 connected in series between terminal 62 and the input node of inverter 78. Each of transistors 86, 87 and 88 has the corresponding gate connected to the corresponding drain to constitute a diode.
In operation, when a signal not more than the power supply potential Vcc is applied through terminal 62, inverter 78 provides the holding signal HD of a high level. Therefore, test mode signal holding circuit 61, in this case, does not hold the signal TM' applied through terminal 58. When the high voltage signal HV over the power supply potential vcc is applied through terminal 62, inverter 78 provides the holding signal HD of a low level. Test mode signal holding circuit 61 holds the test mode signal TM' applied through terminal 58 in response to the signal HD, whereby the held signal is provided as the test mode signal TM. It should be noted that high voltage detecting circuit 60 shown in FIG. 13 can also be employed as high voltage detecting circuit 59 shown in FIG. 11.
As can be seen from the foregoing description, in SRAM's 102 and 103 shown in FIGS. 11 and 12, terminals 58 and 62 having other purposes are used together to externally designate the test mode. The share of terminals 58 and 62 contributes to the prevention of the increase in the external terminal, however, it may cause the problems set forth as in the following.
Since high voltage detecting circuits 59 and 60 have a circuit configuration shown in FIG. 13, a threshold value for determining the high voltage signal HV can be frequently changed by some reasons caused in the manufacturing of the SRAMs. The potential of the high voltage signal HV should be selected higher for performing the designation of the test mode correctly, however, the supply of such high voltage easily destroys a MOS transistor. Therefore, it is necessary to select the potential of the high voltage signal HV within the range which exceeds the power supply potential Vcc but is not so high. As a result, when a threshold value for determining the high voltage is lowered by some reason caused in the manufacturing process, the designation of the test mode may be recognized despite of being not required by the user. Consequently, the test mode operation in the SRAM is started in such a case, thereby being recognized as a malfunction by the user of the SRAM.